As Moore’s law continues unabated, it is predicated that future generation many-cores will feature hundreds, and potentially even thousands, of cores that may be heterogeneous in their processing nature. Consequently, advancements in the chip manufacturing technology and increasing trends of application features have accelerated the growth of advanced computing architectures that need to meet performance-per-power, adaptivity, and reliability requirements. Furthermore, high integration density of nano-scale transistors and roadblock on the voltage scaling result in increased power densities and temperatures on the chip. This leads to the emerging “Dark Silicon” problem, i.e., not all parts of the multi-many-core chip can be simultaneously powered-on at the nominal operating conditions for a given Thermal Design Power (TDP) constraint and cooling technology. High on-chip temperatures also worsen the reliability of multi-/many-cores under peak power and thermal constraints will be presented.
Sitzungszimmer des Dekanats der Fakultät für Informatik, Erzherzog-Johann-PLatz 1, 4. Stock